`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////
////                                                              //// 
////                                                              //// 
////  Parte del proyecto del simple comprobador de memoria        ////  
////                                                              ////
////                                                              //// 
////  Description                                                 //// 
////   - Unir los modulos                                         //// 
////                                                              //// 
////  To Do:                                                      //// 
////   - Conectar los diferentes modulos                          //// 
////                                                              //// 
////  Author(s):                                                  //// 
////      - Sergio Gonzalez Q, sergiogq@hotmail.es                ////
////      - Alejandro Morales, ale3191@gmail.com                  //// 
////                                                              //// 
////////////////////////////////////////////////////////////////////// 
////                                                              //// 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 //// 
////                                                              //// 
//// This source file may be used and distributed without         //// 
//// restriction provided that this copyright statement is not    //// 
//// removed from the file and that any derivative work contains  //// 
//// the original copyright notice and the associated disclaimer. //// 
////                                                              //// 
//// This source file is free software; you can redistribute it   //// 
//// and/or modify it under the terms of the GNU Lesser General   //// 
//// Public License as published by the Free Software Foundation; //// 
//// either version 2.1 of the License, or (at your option) any   //// 
//// later version.                                               //// 
////                                                              //// 
//// This source is distributed in the hope that it will be       //// 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   //// 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //// 
//// PURPOSE.  See the GNU Lesser General Public License for more //// 
//// details.                                                     //// 
////                                                              //// 
//// You should have received a copy of the GNU Lesser General    //// 
//// Public License along with this source; if not, download it   //// 
//// from http://www.opencores.org/lgpl.shtml                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////

module tb_MemorySampleTest;
	
	// Input
	reg clk_i, rst_i;
	reg [1:0] value_write_i; //Valor que el usuario quiere escribir
 
	// Data input-output
	wire [7:0] data_io; 

	//Output
	wire write_o, read_o,segment2_o; 
	wire write_enable_o, output_enable_o;
   wire [3:0] address_o,segment1_o;

			  
	MemorySampleTest tb_memorySampleTest(.clk_i(clk_i),.rst_i(rst_i),.value_write_i(value_write_i),
						.data_io(data_io),.write_o(write_o), .read_o(read_o),
				      .write_enable_o(write_enable_o), .output_enable_o(output_enable_o),
						.address_o(address_o),.segment1_o(segment1_o),.segment2_o(segment2_o));
	
	
	initial begin
		clk_i= 0;
		forever begin
			clk_i = ~clk_i;
			#20;
		end
	end

	initial begin
	
		// Initialize Inputs
		rst_i = 0;
		value_write_i = 3;

		// Wait 100 ns 
		#200;
        
		// Add stimulus here
		rst_i = 1;
		#160;
		rst_i = 0;
	
	end
	
endmodule
